This invention relates to the use of stacked structures (modules) comprising circuitry-carrying layers (IC chips); i.e., each layer has integrated circuitry thereon Such modules provide very densely packaged electronic circuitry. They may be used whenever space conservation in circuitry is desired, e.g., memory units, logic units.
The use of multiple layers in stacked units creates various processing problems, both during the pre stacking chip preparation, and during completion of the stacked unit, or module.
Because it is generally desirable to use IC wafers which are readily purchasable as standard (off-the-shelf) items, the existing on-chip leads require rerouting, in order to permit the eventual stacked unit to function as desired. In prior patents relating to the stacking of IC chips, it has been assumed that chip manufacturers will supply chips having leads suitable for use in stacked modules.
Among the prior relevant patents assigned to the assignee of this application are U.S. Pat. Nos. 4,525,921; 4,646,128; and 4,706,166. The first two listed patents deal with arrangements for avoiding short circuits in the stacked module, and for providing suitable electrical contact points on the access plane(s) of the stacked module, which contact points are available for connection to metallization on the access plane(s). The third listed patent deals with arrangements for bonding terminals on an access plane of a stacked module to terminals on a supporting, circuitry-providing substrate.
Rerouting the leads which are included in commercially available IC wafers has several advantages in the manufacture of stacked chip modules It also creates new problems. The present application deals with those problems, in order to make those advantages available. The assignee of this application has pioneered the use of stacked chips as focal plane modules having photodetectors on the focal plane. For example, see U.S. Pat. Nos. 4,551,629; 4,617,160; and 4,672,737. It also has pioneered the use of stacked chips as electronic modules for other fields, such as computer memory devices. There are significant differences between the two fields of use. The use as computer components may not require the extreme closeness of adjacent leads at the access plane; nor does it have the extremely restrictive power limits encountered in cryogenic photodetector enclosures.
However, a major challenge in providing stacked chips which serve as computer components is the zero tolerance of circuit failures. In a photodetector surveillance system, a certain percentage of outages (non-functioning circuits) is acceptable But in a computer component, every circuit must function properly. In the initial stack, extra chips are included to provide redundancy. This permits a limited number of imperfect chips in a completed stack to be disconnected. But the chips which remain in the operating component must have no circuit outages.
One of the electrical failure points in stacked chip modules has been the T-connections of the aluminum conductors on the chips with the metallization formed on the access plane That problem also provides motivation for the present invention.